As the memory density of a ROM increases, the cell dimensions decrease, resulting in high sheet resistance (R.sub.s) of buried bit lines in the ROM. This is because a decrease in cell dimension causes a decreased width in the bit line which increases bit line sheet resistance. The reduced spacing between the bit lines also results in an unacceptably low punch-through voltage between adjacent bit lines.
FIG. 1 illustrates a buried bit line ROM 20. The ROM 20, for illustrative purposes, comprises a P-type silicon substrate 21. Of course, the ROM could alternatively have an N-type substrate. In this example, a plurality of N.sup.+- type buried bit lines 22 are formed in the ROM 20. Each bit line 22 has a width W and the spacing, or channel, between adjacent bit lines has a length S. A plurality of polysilicon word lines 24 are also formed on the surface of the substrate 21. The ROM 20 comprises a plurality of cells. One such cell 30 is shown in dashed lines in FIG. 1. A cross-sectional view of cell 30 of FIG. 1 taken along the line AA' is shown in FIG. 2.
As seen in FIG. 2, the cell 30 comprises two adjacent buried bit lines 22 which form source and drain regions for the cell. A channel 32 of length S is formed between the two bit lines in the cell 30. A gate oxide layer 36, 37 is formed on top of the substrate 11. The oxide layer is thicker at portions 36 located above the bit lines 22 and thinner at portion 37 located above the channel 32. The thick oxide layer portions 36 are known as field oxide (FOX) regions and the thinner layer portions 37 are known as gate oxide regions. A polysilicon word line 24 is formed over the gate oxide layer 36.
As indicated above, when the bit line width W is too small, the bit line sheet resistance is unacceptably high. In addition, when the bit line spacing S, or channel, is too small, the punch-through voltage between adjacent bit lines is unacceptably low.
Co-pending application Ser. No. 08/092,189 filed on Jul. 14, 1993 and now U.S. Pat. No. 5,430,673 to the same inventors and assigned to the same assignee discloses a buried bit line ROM with low bit line resistance. That memory device and method for making it relate to a memory cell having either the source or drain at the sides and bottom of a trench. Thus, each trench forms either a single source or drain. Also, the fabrication process for the device disclosed therein is different than the process disclosed below.
A buried bit line memory device is also disclosed in U.S. Pat. No. 4,912,535 to Okumura. Okumura discloses a RAM type memory cell having a diffusion region on one side of a trench.
It is an object of the present invention to provide a buried bit line structure and a method for making a buried bit line structure which eliminates the sheet resistance and punch-through voltage problems in high density buried bit line ROMs having small bit line width and spacing.